Analog Devices Inc. AD9656 Quad, 16-Bit ADC

Analog Devices Inc. AD9656 Quad, 16-bit Analog-to-Digital Converters (ADCs) with an on-chip sample-and-hold circuit is designed for ease-of-use in small, low-cost, low power systems. AD9656 delivers at a conversion rate of up to 125MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. AD9656 requires a single 1.8V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. Individual channel power-down is supported and typically consumes less than 2mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the Serial Port Interface (SPI).

Available in a RoHS-compliant, 56-lead LFCSP package and specified over the industrial temperature range of -40°C to +85°C, the AD9656 16-bit ADC is ideal for medical imaging, high-speed imaging, quadrature radio receivers, diversity radio receivers, and portable test equipment.

Features

SNR = 79.9dBFS at 16MHz (V_REF = 1.4V)
SNR = 78.1dBFS at 64MHz (V_REF = 1.4V)
SFDR = 86dBc to Nyquist (V_REF = 1.4V)
JESD204B Subclass 1 coded serial digital outputs
Flexible analog input range: 2.0Vp-p to 2.8Vp-p
1.8V supply operation
Low power of 197mW per channel at 12MSPS (two lanes)
DNL = ±0.6LSB (V_REF = 1.4V)
INL = ±4.5LSB (V_REF = 1.4V)
650MHz analog input bandwidth, full power
Serial port control
Full chip and individual channel power-down modes
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Standby mode

Product Highlights:
- Small footprint:
  - Four ADCs are contained in a small, 8mm × 8mm package
- On-chip Phase-Locked Loop (PLL):
  - Allows users to provide a single ADC sampling clock
  - PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock
- Configurable JESD204B output block supports up to 6.4Gbps per lane
- JESD204B output block supports one, two, and four-lane configurations
- Low power of 198mW per channel at 125MSPS, two lanes
- SPI control offers a wide range of flexible features to meet specific system requirements