Astera Labs PT4161L PCI Express® Gen-4 x16 Smart Retimer
Astera Labs PT4161L PCI Express® Gen-4 x16 Low-Latency Smart Retimer integrates seamlessly between a Root Complex and End Point(s) extending the reach by >28dB at 16GT/s. The PT4161L is compliant to all PCIe 4.0 rates and retimer functional requirements while enabling more system topologies, and a lower total solution cost. The PT4161L eliminates signal integrity issues for PCI-Express (PCIe) 4.0 interconnects in data-centric applications and is ideal for space-restricted applications like system boards and riser cards.
The Astera Labs PT4161L PCI Express Retimer has an innovative protocol-non-disruptive low-latency architecture that significantly reduces latency while being transparent to system software. This architecture participates in Link equalization with the root complex and endpoint(s) to optimize Link performance. The PT4161L can independently adapt its latency to maximize performance during normal operational Link-state (L0) while maintaining protocol interoperation.
The PT4161L supports a wide variety of end points and port configurations by subdividing to one x16 Link, two x8 Links, four x4 Links, eight x2 Links, and more. In-band (Receiver margining) and out-of-band (SMBus) methods are accessible through per-Link diagnostics information, such as Link state history and electrical margin. Each Link operates independently.
The PT4161L features a standard PCIe 100MHz HCSL input clock, and provides a 100MHz HCSL output clock to drive other Retimer devices or PCIe components in the system.
The PT4161L Smart Retimer offers a compact design, minimal supporting circuitry, and integrated AC-coupling capacitors. The pinout is based on the Intel Retimer Supplemental Specification and uses an 8.9mm x 22.8mm Flip-Chip CSP package.
Features
- Compatible with PCIe Gen-4/3/2/1
- 16GT/s, 8GT/s, 5GT/s, and 2.5GT/s Data rates with automatic link equalization
- Low-latency mode enables cache-coherent links
- 16 Lanes with flexible link bifurcation including 1x16, 2x8, 4x4, 8x2, and others
- Extends reach by >28db at 16gt/s enabling low cost pcb materials and connectors
- Receiver and transmitter performance exceeds PCI Express base specification requirements
- No system software required
- BGA package footprint optimized for board routing
- Integrated AC-coupling capacitors reduce solution size and improves signal integrity performance
- Supports hot plug and hot unplug
- Supports lane margining at the receiver for both timing and voltage
- Supports SRIS, SRNS, and common clock systems
- Supports slave loopback
- Supports systems with lane reversal and implements automatic polarity correction
- Low-power advanced CMOS process
- HCSL Reference clock output eliminates clock buffers to drive downstream PCIe components
- Advanced in-band and out-of-band diagnostics for fleet management, large-scale server deployments
- Full-featured C and Python SDKs for rapid integration of advanced diagnostics features
- Device configuration through SMBus or EEPROM
- IEEE 1149.6 AC-JTAG Boundary scan
- Full portfolio of pin- and register-compatible retimers enables easy performance scaling up to PCI Express Gen-5
Applications
- Server and high-performance PC motherboards
- PCIe Riser and add-in cards
- Server-to-server cabled interfaces
- NVMe JBOFs, GPU/Deep-learning accelerators
Videos
Typical Application
