BittWare XUP-P3R FPGA Accelerator Card

BittWare XUP-P3R FPGA Accelerator Card is a 3/4-length PCIe x16 card based on the Xilinx Virtex UltraScale+ FPGA. The Xilinx Virtex UltraScale+ FPGA delivers high-performance, high-bandwidth, and reduced latency for systems demanding massive data flow and packet processing.

The BittWare XUP-P3R FPGA Accelerator Card provides extensive memory configurations, including support for up to 512 GBytes of memory. This includes sophisticated clocking and timing options and four front panel QSFP cages, each supporting up to 100Gbps (4x25), as well as 100GbE. SEP (serial expansion port) allows the XUPP3R to be expanded for an additional PCIe Gen3 x16 slot, supplementary 4 QSFPs, or connection between two XUPP3Rs.

The XUP-P3R Card integrates a Board Management Controller (BMC) for advanced system monitoring. This allows platform integration and management to be greatly simplified. These features make the XUP-P3R ideal for a wide range of data center applications, including network processing and security, acceleration, storage, broadcast, and SigInt.

Features

4x 100GbE via 4 QSFP28
Up to 512 GBytes DDR4
2.5 million LCs FPGA by Xilinx up to VU9P

Specifications

FPGA
- Virtex UltraScale+ VU9P
- Core speed grade – 2
On-board Flash
- Flash memory for booting FPGA
External memory
- 4 DIMM sites, each supporting
  - Up to 128 GBytes DDR4 x72 with ECC
  - Up to 576 Mbits dual QDR-II+ x18 (2 independent 288 Mbit banks)
Host interface
- x16 Gen3 interface directly to FPGA
USB ports
- Micro USB 2.0 for debugging and programming FPGA and Flash
Serial expansion port (SEP)
- Expansion interface to FPGA via 20x GTY transceivers (optional; requires the second slot)
- 14x GPIO signals to the FPGA
Board Management Controller
- Voltage, current, temperature monitoring
  - Power sequencing and reset
- Field upgrades
- FPGA configuration and control
- Clock configuration
- I²C bus access
- USB 2.0
- Voltage overrides
FPGA development
- FPGA Examples – example Vivado projects

QSFP cages
- 4 QSFP28 (zQSFP) cages on the front panel connected directly to FPGA via 16 transceivers
- Each supports 100GbE, 40GbE, 4x 25GbE, or 4x 10GbE and can be combined for 400GbE
Cooling
- Double-width active fan and heatsink - standard
- Double-width passive heatsink - optional
- Double-width advanced passive cooling with heat pipes - optional
Electrical
- On-board power derived from a 12V PCIe slot & an AUX connector (6-pin)
- Power dissipation is application dependent
Environmental
- Operating temperature 5°C to 35°C
Form factor
- 3/4-length, standard-height PCIe dual-slot board
- 9.4 x 4.37 inches
Application development
- HDL/Verilog
  - BittWorks II Toolkit – host, command, and debug tools for BittWare hardware
  - Xilinx Vivado^® Design Suite
- OpenCL - Xilinx SDAccel Development Environment, SDAccel Platform Release, and pre-built examples for XUP-P3R